NDLI: Hardware Design Space Exploration with a New Dimension -- IP Protection Robustness

Content Provider	IEEE Xplore Digital Library
Author	Qiang Liu Haie Li
Copyright Year	2015
Description	Author affiliation: Sch. of Electron. Inf. Eng., Tianjin Univ., Tianjin, China (Qiang Liu; Haie Li)
Abstract	Design space exploration (DSE) is now an important phase of the SoC design process, in order to realize high-efficiency design. In conventional DSE, design metrics such as speed, power and area are extensively used to evaluate various design options. As IP-reuse is widely adopted, protection of hardware IPs has been paid more and more attention at advanced design processes. This paper considers IP protection as a new dimension of DSE. The approach analytically models power consumption, resource usage, execution time and IP protection robustness of hardware designs, and formulates the expanded multi-objective DSE as a constrained optimization problem. The resultant design from solving the optimization problem achieves trade-offs between design performance and IP protection robustness. The approach is validated on three application kernels, demonstrating the capability of the approach in finding optimized designs, which actually locates in the Pareto frontier of the design space.
Starting Page	599
Ending Page	605
File Size	434655
Page Count	7
File Format	PDF
e-ISBN	9781467380355
DOI	10.1109/DSD.2015.19
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-08-26
Publisher Place	Portugal
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Robustness IP networks Power demand Hardware Clocks Optimization Time factors
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A new watermarking method for soft IP protection

Optimum power/performance pipeline depth

A method to abstract RTL IP blocks into C++ code and enable high-level synthesis

IP watermark verification based on power consumption analysis

Energy aware management of resilient networks with shared protection

System level optimization and design space exploration for low power

Design-space exploration of power-aware on/off interconnection networks

A methodology for self correction scheme based fast multi criterion exploration and architectual synthesis of data dominated applications

CoreVA: A Configurable Resource-Efficient VLIW Processor Architecture

Hardware Design Space Exploration with a New Dimension -- IP Protection Robustness

Similar Documents

A new watermarking method for soft IP protection

Optimum power/performance pipeline depth

A method to abstract RTL IP blocks into C++ code and enable high-level synthesis

IP watermark verification based on power consumption analysis

Energy aware management of resilient networks with shared protection

System level optimization and design space exploration for low power

Design-space exploration of power-aware on/off interconnection networks

A methodology for self correction scheme based fast multi criterion exploration and architectual synthesis of data dominated applications

CoreVA: A Configurable Resource-Efficient VLIW Processor Architecture

Hardware Design Space Exploration with a New Dimension -- IP Protection Robustness