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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Reiter, S. Viehl, A. Bringmann, O. Rosenstiel, W. |
| Copyright Year | 2015 |
| Description | Author affiliation: FZI Forschungszentrum Inf., Karlsruhe, Germany (Reiter, S.; Viehl, A.) || Univ. Tubingen, Tubingen, Germany (Bringmann, O.; Rosenstiel, W.) |
| Abstract | This paper presents an approach on extending virtual prototyping, commonly used for system verification and design space exploration, for safety analysis. Virtual prototyping will enhance safety analysis, overcoming the challenges resulting from the ever-increasing number of safety-related, complex, interconnected electronic systems. The presented integral fault injection framework enables safety analysis in combination with established system verification methods. It consists of a fault behavior specification methodology and the corresponding, reusable injection tool, with focus on seamless applicability in between functional models in early concept phases and low-level structural models in late design phases. Our approach works with third party compilers and simulators while providing a minimal intrusive approach using existing models. Selected use cases at gate, register-transfer and functional level demonstrate the usage of the approach. |
| Starting Page | 534 |
| Ending Page | 538 |
| File Size | 479688 |
| Page Count | 5 |
| File Format | |
| e-ISBN | 9781467380355 |
| DOI | 10.1109/DSD.2015.83 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2015-08-26 |
| Publisher Place | Portugal |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Safety Registers Monitoring Clocks Unified modeling language Logic gates Probes Safety analysis System simulation Fault injection Error modelling SystemC |
| Content Type | Text |
| Resource Type | Article |
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