NDLI: Hardware Support for Cost-Effective System-Level Protection in Multi-core SoCs

Content Provider	IEEE Xplore Digital Library
Author	Kornaros, G. Christoforakis, I. Tomoutzoglou, O. Bakoyiannis, D. Vazakopoulou, K. Grammatikakis, M. Papagrigoriou, A.
Copyright Year	2015
Description	Author affiliation: Inf. Eng. Dept., Technol. Educ. Inst. of Crete, Iraklio, Greece (Kornaros, G.; Christoforakis, I.; Tomoutzoglou, O.; Bakoyiannis, D.; Vazakopoulou, K.; Grammatikakis, M.; Papagrigoriou, A.)
Abstract	The increasing adoption of multi-core Systems-on-Chip (SoC) in critical systems has turned security into an important design requirement. In addition to making a SoC tamper-resistant by embedding cryptographic solutions, in order to make a system robust, we need to control the level of access to the critical functions and capabilities. We propose a hardware protection architecture to enhance a traditional SoC platform in terms of protection. These hardware enhancements focus on isolating physical memory compartments by applying access rules, thus we allow dynamic security policies to be enforced at the hardware for protection against untrustworthy hardware or software components. We present and analyze an implementation of a prototype that allows sixteen concurrently active protection domains at a system cost of less that three percent and negligible operational overhead.
Starting Page	41
Ending Page	48
File Size	871500
Page Count	8
File Format	PDF
e-ISBN	9781467380355
DOI	10.1109/DSD.2015.65
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-08-26
Publisher Place	Portugal
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Security Hardware System-on-chip Registers Program processors Computer architecture Embedded Systems Security NoC Security Memory Protection
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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