NDLI: Performance Evaluation of Instruction Set Extensions for Long Integer Modular Arithmetic on a SPARC V8 Processor

Content Provider	IEEE Xplore Digital Library
Author	Grossschadl, J. Tillich, S. Szekely, A.
Copyright Year	2007
Description	Author affiliation: Inst. for Appl. Inf. Process. & Commun., Graz Univ. of Technol., Graz, Austria (Grossschadl, J.; Tillich, S.; Szekely, A.)
Abstract	Many important algorithms for public-key cryptography rely on computation-intensive arithmetic operations like modular exponentiation on very long integers, typically in the range of 512 and 2048 bits. Modular exponentiation is generally realized through a sequence of modular multiplications and spends the majority of execution time in simple inner loops. Speeding up these performance-critical inner loop operations with custom instructions has, therefore, a significant impact on the total execution time of public-key cryptosystems. In this paper we analyze the performance of instruction set extensions for long integer arithmetic on a SPARC V8 processor. We discuss various implementation options and optimization opportunities for both modular multiplication and exponentiation. In particular, we introduce a partial loop unrolling (PLU) technique for modular multiplication which allows to achieve large performance gains at the cost of a moderate increase in code size, while maintaining the full flexibility of a "rolled-loop" implementation. In addition, we study window methods for modular exponentiation and analyze their impact on performance and memory requirements. Our experimental results, obtained with an FPGA prototype of the LEON-2 SPARC V8 core, show that a full 1024-bit modular exponentiation can be performed in about 12.5 ldr $10^{6}$ clock cycles, which is a reasonable value for embedded devices like smart cards or sensor nodes.
Starting Page	680
Ending Page	689
File Size	236940
Page Count	10
File Format	PDF
ISBN	9780769529783
DOI	10.1109/DSD.2007.4341542
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-08-29
Publisher Place	Germany
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Arithmetic Public key cryptography Performance analysis Performance gain Costs Field programmable gate arrays Prototypes Clocks Smart cards Intelligent sensors
Content Type	Text
Resource Type	Article

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