NDLI: A Low Power Information Redundant Concurrent Error Detecting Asynchronous Processor

Content Provider	IEEE Xplore Digital Library
Author	Marshall, M. Russell, G.
Copyright Year	2007
Description	Author affiliation: Sch. of Electr., Univ. of Newcastle upon Tyne, Newcastle upon Tyne, UK (Marshall, M.; Russell, G.)
Abstract	As a result of advances in technology shrinking device dimensions, the occurrence of transient errors is increasing. This together with the concomitant reduction in supply voltages has decreased noise margins causing system reliability to be reduced, at a time when electronic systems are being used increasingly in 'safety critical' applications. Previous work has demonstrated that an information redundant Concurrent Error Detection (CED) scheme using Dong's Code can be applied efficiently to a processor using an asynchronous design style incurring area overheads of approximately 12% [1] when placed on silicon. This paper furthers the above work by extending the capabilities of the processor to include the multiplication function also guarded by a CED scheme, permitting the processor to be used in a wider range of applications; e.g. DSP. The paper also demonstrates that a reduction in power of 22% can be achieved by utilising an asynchronous design style rather than its synchronous counterpart. Furthermore, the power overhead for the asynchronous CED processor was found to be 5% less than that of the synchronous processor without CED. Asynchronous design style is also known to have the inherent benefit of not requiring difficult to design, global timing clock trees and networks. Previous work has also demonstrated that approximately, 25% area savings can be made when comparing Dong's Code to a Berger Code CED scheme on the multiplier function [2]. Through the implementation of a larger number of operations within the ALU, all protected by the same information redundant code, further savings can be made through reuse of common blocks, as codes often share many similarities within their prediction equations. With lower power dissipation and a reduced area overhead, compared to its synchronous counterpart, this makes the asynchronous CED circuit attractive and viable for reliable mobile computation. This paper also extends the work with the implementation of a synchronous and asynchronous processor, with and without CED on a FPGA.
Starting Page	649
Ending Page	656
File Size	432856
Page Count	8
File Format	PDF
ISBN	9780769529783
DOI	10.1109/DSD.2007.4341536
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-08-29
Publisher Place	Germany
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Computer errors Voltage Noise reduction Reliability Safety Silicon Digital signal processing Timing Clocks Protection
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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