NDLI: Low-Complexity Architectures of a Decoder for IEEE 802.16e LDPC Codes

Content Provider	IEEE Xplore Digital Library
Author	Gentile, G. Rovini, M. Fanucci, L.
Copyright Year	2007
Description	Author affiliation: Dept. of Inf. Eng., Univ. of Pisa, Pisa, Italy (Gentile, G.; Rovini, M.; Fanucci, L.)
Abstract	Low-density parity-check (LDPC) codes have recently been included as error-correcting codes in IEEE 802.16e, for wireless metropolitan area networks. This paper proposes a flexible, low-complexity LDPC decoder fully compliant with all 114 codes defined by the standard. The decoder runs the layered decoding algorithm to increase the convergence speed, and relies on a semi-parallel implementation with serial processing units working in pipeline to reduce the latency. Particularly, two different architectures are considered, and their RTL/memory complexity tradeoffs are analyzed. The resulting design yields a throughput ranging from 93 to 497 Mbps by means of 15 iterations at the clock frequency of 400 MHz. Synthesis on 65 nm CMOS technology, shows a chip area less than 0.59 $mm^{2},$ despite the high flexibility, which compares favourably with similar implementations.
Starting Page	369
Ending Page	375
File Size	340200
Page Count	7
File Format	PDF
ISBN	9780769529783
DOI	10.1109/DSD.2007.4341494
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-08-29
Publisher Place	Germany
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Decoding Parity check codes CMOS technology Error correction codes Wireless LAN Metropolitan area networks Code standards Convergence Pipelines Delay
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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