NDLI: Application-Specific Topology Design Customization for STNoC

Content Provider	IEEE Xplore Digital Library
Author	Palermo, G. Silvano, C. Mariani, G. Locatelli, R. Coppola, M.
Copyright Year	2007
Description	Author affiliation: Dipt. di Elettronica e Inf., Politecnico di Milano, Milan, Italy (Palermo, G.; Silvano, C.)
Abstract	Customized network-oriented communication architectures have recently become a must to support high bandwidth SoCs. To this end, a corresponding communication design flow is necessary to support the design space exploration of complex SoCs with tight design constraints. In order to exploit the benefits introduced by the NoC approach for the on-chip communication, the paper presents a Pareto Simulated Annealing (PSA) approach for the customization of the network topology. The proposed PSA approach has been applied to STNoC, the Network on-Chip developed by STMicroelectronics. Starting from the ring topology, the proposed application-specific design flow tries to find a set of customized topologies (optimized in terms of performance and area/energy overhead) by adding custom links up to the spidergon topology.
Starting Page	547
Ending Page	550
File Size	408523
Page Count	4
File Format	PDF
ISBN	9780769529783
DOI	10.1109/DSD.2007.4341522
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-08-29
Publisher Place	Germany
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Network topology Network-on-a-chip Bandwidth Telecommunication traffic Design methodology Informatics Space technology Space exploration Simulated annealing Design optimization
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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