NDLI: Alternatives in Designing Level-Restoring Buffers for Interconnection Networks in Field-Programmable Gate Arrays

Content Provider	IEEE Xplore Digital Library
Author	Miller, S. Sima, M. McGuire, M.
Copyright Year	2007
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Univ. of Victoria, Victoria, BC, Canada (Miller, S.; Sima, M.; McGuire, M.)
Abstract	Programmable routing and logic in field-programmable gate arrays are implemented using nMOS pass transistors. Since the threshold voltage drop across an nMOS device degrades the high logic value, causing the pMOS transistor of the downstream buffer to not turn fully off, this approach suffers from static power consumption and reduced noise margins. The standard pMOS transistor pull-up in an active feedback of an inverter reduces the static power consumption, but degrades the switching time and/or active power consumption. We propose a circuit technique to build level-restoring buffers, which improves the propagation delay or active power consumption at a tiny area penalty. Our main idea is to replicate the nMOS element of the downstream buffer, where each replica is driven by a signal that originates from earlier stages of the nMOS-tree multiplexer. This way, when passing high logic values, signals from earlier stages directly drive the downstream buffer improving the delay or the slope of the transition edge. The passing of low logic values is still performed in the original way by the nMOS tree and the pMOS element of the downstream buffer. The simulations indicate an average improvement of the composite metric area-delay-energy product of 25% versus the standard approach across 180 nm, 130 nm, and 90 nm technologies.
Starting Page	138
Ending Page	146
File Size	266680
Page Count	9
File Format	PDF
ISBN	9780769529783
DOI	10.1109/DSD.2007.4341461
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-08-29
Publisher Place	Germany
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Multiprocessor interconnection networks Field programmable gate arrays MOS devices Energy consumption Logic devices Programmable logic arrays Degradation MOSFETs Routing Logic gates
Content Type	Text
Resource Type	Article

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