NDLI: Multi-log processor - towards scalable event-driven multiprocessors

Content Provider	IEEE Xplore Digital Library
Author	Viswanath, V.
Copyright Year	2004
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA (Viswanath, V.)
Abstract	We present the multi-log processors, an event-driven multiprocessor. The functionality of the processor is defined by the triggering of events, maintained in a single event queue. The key feature of multi-log is that the entire register file and the event queue are shared. We describe the network architecture of the multi-log and discuss optimum layout schemes. This article describes two scalable event-driven multiprocessor architectures, the multi-log I and the multi-log II, and compares their VLSI complexities (gate delays, wire-length delays, and area). Both multiprocessors are implemented by a large collection of ALUs with controllers and on chip speculative L0 caches (together called logPs) connected together by a network of parallel-prefix tree circuits. A fat-tree network connects an interleaved memory to the logPs. These networks provide superscalar uniprocessor-like functionality, including register renaming, out-of-order event execution, and speculative event execution. Given 1 billion transistors on a single chip, the multi-log I architecture would have 256 logPs on chip, while the multi-log II architecture would allow for 1024 logPs on chip. We propose a new strategy to handle non-local events by introducing a mechanism to allow event transfers over the just described network, by means of event stealing. We also propose an instruction set architecture for the multi-log processor and give a programming model for event-driven applications. Scheduling events and stealing events are implemented in software. We suggest some innovative schemes for their implementation and analysis.
Starting Page	279
Ending Page	286
File Size	446997
Page Count	8
File Format	PDF
ISBN	0769522033
DOI	10.1109/DSD.2004.1333288
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-08-31
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Registers Circuits Parallel programming Very large scale integration Delay Cache memory Maintenance engineering Network-on-a-chip Out of order Computer architecture
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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