NDLI: Memory aware HLS and the implementation of ageing vectors

Content Provider	IEEE Xplore Digital Library
Author	Corre, G. Senn, E. Julien, N. Martin, E.
Copyright Year	2004
Description	Author affiliation: South Brittany Univ., Lorient, France (Corre, G.; Senn, E.; Julien, N.; Martin, E.)
Abstract	We introduce a new approach to take into account the memory architecture and the memory mapping in behavioral synthesis. We formalize the memory mapping as a set of constraints for the synthesis, and defined a memory constraint graph and an accessibility criterion to be used in the scheduling step. We present a new strategy for implementing signals (ageing vectors). We formalize the maturing process and explain how it may generate memory conflicts over several iterations of the algorithm. The final compatibility graph indicates the set of valid mappings for every signal. Several experiments are performed with our HLS tool GAUT. Our scheduling algorithm exhibits a relatively low complexity that permits to tackle complex designs in a reasonable time.
Starting Page	88
Ending Page	95
File Size	406936
Page Count	8
File Format	PDF
ISBN	0769522033
DOI	10.1109/DSD.2004.1333262
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-08-31
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	High level synthesis Aging Job shop scheduling Signal synthesis Scheduling algorithm Algorithm design and analysis Memory architecture Memory management Signal processing algorithms Signal processing
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Memory aware HLS and the implementation of ageing vectors

High-level DSP synthesis using the COMET design system

Memory aware HLS and the implementation of ageing vectors

Memory accesses management during high level synthesis

Dedicated DSP architecture synthesis using the MARS design system

Scheduling and Binding Algorithms for High-Level Synthesis

Memory aware HLS and the implementation of ageing vectors (2006)

Algorithms for high-level synthesis

Valid transformations: a new class of loop transformations for high-level synthesis and pipelined scheduling applications

Memory aware HLS and the implementation of ageing vectors

Similar Documents

Memory aware HLS and the implementation of ageing vectors

High-level DSP synthesis using the COMET design system

Memory aware HLS and the implementation of ageing vectors

Memory accesses management during high level synthesis

Dedicated DSP architecture synthesis using the MARS design system

Scheduling and Binding Algorithms for High-Level Synthesis

Memory aware HLS and the implementation of ageing vectors (2006)

Algorithms for high-level synthesis

Valid transformations: a new class of loop transformations for high-level synthesis and pipelined scheduling applications

Memory aware HLS and the implementation of ageing vectors