NDLI: Investigating available instruction level parallelism for stack based machine architectures

Content Provider	IEEE Xplore Digital Library
Author	Huibin Shi Bailey, C.
Copyright Year	2004
Description	Author affiliation: Dept. of Comput. Sci., York Univ., UK (Huibin Shi; Bailey, C.)
Abstract	Stack architectures have attracted much renewed research in recent years, due largely to the arrival of the JAVA programming language for Internet, and more recently in embedded applications. However, instruction level parallelism (ILP) has not yet received significant attention with respect to such machines. We have developed a stack code viewer/analyzer tool to analyze available ILP in stack assembler-code, together with the UTSA simulator, under unlimited software and hardware resource configurations. Results for basic block analysis reveal marginal speedups of available ILP over the serial execution in the absence of mechanisms for branch speculation or code optimization. Results for superblock and loop unrolling techniques show that more significant improvements can be made to available parallelism where effort is directed. An experiment is also presented to highlight the significance of branch prediction. In all tests, our stack code viewer/analyzer tool can graphically represent the scheduling result of each basic block.
Starting Page	112
Ending Page	120
File Size	345565
Page Count	9
File Format	PDF
ISBN	0769522033
DOI	10.1109/DSD.2004.1333266
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-08-31
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Parallel processing Computer architecture Java Computer languages Internet Computer science Application software Assembly Analytical models Software tools
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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