NDLI: Pipeline-level control of self-resetting pipelines

Content Provider	IEEE Xplore Digital Library
Author	Ejnioui, A. Alsharqawi, A.
Copyright Year	2004
Description	Author affiliation: departmet of Electr. & Comput. Eng., Univ. of Central Florida, Orlando, FL, USA (Ejnioui, A.; Alsharqawi, A.)
Abstract	In this paper, we present a synchronization approach to support data flow in clockless designs using single-rail encoding. This approach is based on self-resetting stage logic in which a pipeline stage resets itself before starting the next execution cycle. As such, a stage goes through a reset phase when its output is null, and an evaluate phase when its output is the result of the evaluation of its inputs. To insure correct operation, data flow from one stage to another when the preceding stage is in the evaluate phase while the following stage is in the reset phase. To support this data flow, a latch-based synchronization mechanism is proposed. This mechanism yields an efficient and simple uni-directional handshaking scheme emanating from the last stage in the pipeline back towards the remaining stages of the pipeline. This handshaking scheme is extended to handle the join and forks of data flows encountered in non-linear pipelines. A concept design of a four-bit 16-stage pipeline is presented to illustrate the inner workings of self-resetting stage logic and its data-flow synchronization mechanism. The signal timing analysis of this pipeline reveals that the duration of the evaluate and reset phase remains constant in the stages located to the left of the last stage in the pipeline. As a result, the last stage operates as a pulse generator with which the remaining stages of the pipeline synchronize in such a way that neighboring stages operates in opposing phases at each cycle of execution.
Starting Page	342
Ending Page	349
File Size	355748
Page Count	8
File Format	PDF
ISBN	0769522033
DOI	10.1109/DSD.2004.1333295
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-08-31
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Pipelines Clocks Frequency synchronization Logic design Circuit synthesis Signal design Signal synthesis Protocols CMOS logic circuits Encoding
Content Type	Text
Resource Type	Article

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