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Memory aware HLS and the implementation of ageing vectors
| Content Provider | Hyper Articles en Ligne (HAL) |
|---|---|
| Author | Corre, Gwenolé Senn, Eric Julien, Nathalie Martin, Eric |
| Abstract | We introduce a new approach to take into account the memory architecture and the memory mapping in behavioral synthesis. We formalize the memory mapping as input constraints of our synthesis tool. A Memory Constraint Graph and an accessibility criterion are used during the scheduling step. Then, a new strategy for implementing signals (ageing vectors) is introduced. We formalize the maturing process and explain how it may generate memory conflicts over several iterations of the algorithm. The final Compatibility Graph indicates the set of valid mappings for every signal. Several experiments are performed with our HLS tool GAUT. |
| Ending Page | 95 |
| Page Count | 8 |
| Starting Page | 88 |
| File Format | |
| Language | English |
| Publisher | EUROMICRO |
| Publisher Date | 2004-01-01 |
| Access Restriction | Open |
| Subject Keyword | HLS Memory synthesis scheduling info Computer Science [cs] Hardware Architecture [cs.AR] |
| Content Type | Text |
| Resource Type | Article |
