NDLI: Low-leakage WSe2 FET gate-stack using titanyl phthalocyanine seeding layer for atomic layer deposition of Al2O3

Content Provider	IEEE Xplore Digital Library
Author	Fathipour, S. Jun Hong Park Kummel, A. Seabaugh, A.
Copyright Year	2015
Description	Author affiliation: Dept. of Electr. Eng., Univ. of Notre Dame, Notre Dame, IN, USA (Fathipour, S.; Seabaugh, A.) \|\| Dept. of Chem. & Biochem., Univ. of California, San Diego, La Jolla, CA, USA (Kummel, A.) \|\| Mater. Sci. & Eng. Program, Univ. of California, San Diego, La Jolla, CA, USA (Jun Hong Park)
Abstract	Summary form only given. The fabrication of top-gated transition metal dichalchogenide (TMD) field-effect transistors (FETs), requires a uniform and pinhole-free gate dielectric. For realization of TMD tunnel FETs (TFETs) a high-k gate dielectric with subnanometer equivalent oxide thickness (EOT) is required. However, deposition of a thin, uniform high-k dielectric on a TMD surface without functionalization is challenging [1]. This is due to the lack of dangling bonds on the TMD surface. In this report, titanyl (TiO) phthalocyanine $(C_{32}H_{18}N_{8}),$ TiOPc, is used successfully as a seeding layer on $WSe_{2}$ to enable the atomic layer deposition of $Al_{2}O_{3}.$ TiOPc is an organic semiconductor with a band gap of approximately 2 eV in air [2]. We demonstrate the first top-gated TMD FET with an EOT as low as 2.2 nm $(ε_{Al2O3}$ = 9) and a gate leakage current density of 0.2 $pA/μm^{2}$ at 1 V gate bias. The best prior report we have found, by Liu [3] on $MoS_{2},$ achieved an EOT of 6.9 nm with a gate leakage current density of 2 $pA/μm^{2}.$ As a point of reference the ITRS [4] targets an ultimate EOT for CMOS approaching 0.4 nm with a current density below 0.25 $pA/μm^{2}.$ Here, we compare the electrical characteristics of top-gated TiOPc-seeded $Al_{2}O_{3}$ $WSe_{2}$ FETs against the characteristics of the same transistor with an ALD $Al_{2}O_{3}$ back gate. We also report the improvements obtained by post-deposition high vacuum annealing.
Sponsorship	IEEE Electron Devices Soc.
Starting Page	213
Ending Page	214
File Size	1133607
Page Count	2
File Format	PDF
ISBN	9781467381345
e-ISBN	9781467381352
DOI	10.1109/DRC.2015.7175641
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-06-21
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Logic gates Aluminum oxide Field effect transistors Modulation Surface treatment Leakage currents
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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