NDLI: Subtractive plasma-etch process for patterning high performance ZnO TFTs

Content Provider	IEEE Xplore Digital Library
Author	Donigan, T. Langley, D. Schuette, M. Crespo, A. Walker, D. Tetlak, S. Leedy, K. Jessen, G.
Copyright Year	2015
Description	Author affiliation: Air Force Res. Lab., Wright-Patterson AFB, OH, USA (Schuette, M.; Crespo, A.; Walker, D.; Tetlak, S.; Leedy, K.; Jessen, G.) \|\| Air Force Inst. of Technol., Wright-Patterson AFB, OH, USA (Donigan, T.; Langley, D.)
Abstract	Fig 2 shows a cross sectional SEM image of the channel area after etching tungsten prior to stripping the PMMA etch mask. The thickness of the ZnO film measured ~52 nm, both in the channel area and underneath the source/drain pads, indicating that the ZnO film was not thinned during the plasma-etch process. Fig 3(a) and (b) show the $I_{D}-V_{D}$ output characteristics of a ZnO TFT with a 155 nm and 425 nm channel, respectively. The maximum observed drain current density $(I_{D})$ and transconductance $(g_{m})$ for the 155 nm devices was 830 mA/mm and 121 mS/mm, respectively. However, the devices do not saturate at high $V_{D}$ values, due to lateral breakdown limitations of the short channels. Fig 3(c) shows $I_{D}$ plotted as a function of $V_{G}$ on both a log- and linear-scale for devices operating in the linear region with measured channel lengths of 155, 215, 325 and 425 nm. The devices show a near linear dependence on $I_{D}$ versus $L_{C}.$ However, a negative shift in the on-voltage $(V_{on}),$ defined as the gate voltage when $I_{D}$ begins its initial increase the $log(I_{D})-V_{G}$ plot [4] is observed as $L_{C}$ is decreased. Fig 4(a) shows the extracted on-resistance $(R_{on})$ plotted as a function of channel length. From the data, the total parasitic source/drain resistance $(R_{SD})$ can be extracted by gated-TLM method [5], shown in Fig 4(b). The devices exhibit a width normalized $R_{SD}$ of 2.1 Ω·mm indicating the tungsten/ZnO interface resistance is low.
Sponsorship	IEEE Electron Devices Soc.
Starting Page	199
Ending Page	200
File Size	754381
Page Count	2
File Format	PDF
ISBN	9781467381345
e-ISBN	9781467381352
DOI	10.1109/DRC.2015.7175632
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-06-21
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Logic gates Switching circuits Gold Nickel DH-HEMTs Films Plasma measurements
Content Type	Text
Resource Type	Article

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