NDLI: First demonstration of GaN-based vertical nanowire FET with top-down approach

Content Provider	IEEE Xplore Digital Library
Author	Young-Woo Jo Dong-Hyeok Son Dong-Gi Lee Chul-Ho Won Jae Hwa Seo In Man Kang Jung-Hee Lee
Copyright Year	2015
Description	Author affiliation: Sch. of Electron. Eng., Kyungpook Nat. Univ., Daegu, South Korea (Young-Woo Jo; Dong-Hyeok Son; Dong-Gi Lee; Chul-Ho Won; Jae Hwa Seo; In Man Kang; Jung-Hee Lee)
Abstract	Summary form only given. GaN-based field effect transistors (FETs) are widely used in power switching and amplifier application due to its superior material properties such as wide band-gap energy, high breakdown field, and high electron saturation velocity, which results in high output current and high breakdown voltage [1]. On the other hand, nanowire transistors are extensively investigated to improve device performance such as fin-shaped FETs (FinFETs), lateral and vertical type nanowire FETs [2 - 4]. Especially, vertical nanowire FETs (VNFETs) are currently being evaluated as a promising device technology due to its negligible trapping and leakage from the buffer layer, wrap-gated structure and possibility of very short gate length (below 20 nm). VNFETs using Si, InAs and InGaAs materials were already introduced. However, GaN-based VNFETs have been never fabricated due to difficulty in obtaining vertical nanowire structure with high aspect ratio and their complex fabrication process. In this work, we fabricated the GaN-based VNFET, for the first time, by combining conventional e-beam lithography and dry etching technique with strong anisotropic TMAH wet etching.
Sponsorship	IEEE Electron Devices Soc.
Starting Page	35
Ending Page	36
File Size	944446
Page Count	2
File Format	PDF
ISBN	9781467381345
e-ISBN	9781467381352
DOI	10.1109/DRC.2015.7175539
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-06-21
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Logic gates Tin Gallium nitride Wet etching Nanoscale devices Nanostructures
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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