NDLI: A Communicating Petri Net Model for the Design of Concurrent Asynchronous Modules

Content Provider	IEEE Xplore Digital Library
Author	de Jong, G.G. Lin, B.
Copyright Year	1994
Description	Author affiliation: IMEC, Leuven, Belgium (de Jong, G.G.)
Abstract	Current asynchronous tools are focussed mainly on the design of a single interface module. In many applications, one must design interacting interface modules that potentially communicate in complex and intricate ways. When designing communicating asynchronous modules, several difficult problems arise. First, even if each individual module can be synthesized correctly, according to the environmental assumptions specified for that module, the composition of the communicating modules may not work properly. Thus, one needs to have a way to model how the modules interact with each other, and to verify that their cooperation is consistent. In addition, means should be provided for communication and synchronization at a level higher than signal transitions, and for exploiting the communicating nature of these modules in optimization. This paper proposes a communicating Petri net model for describing communicating asynchronous modules. Each module is modeled by means of a labeled Petri net that extends the widely used Signal Transition Graph model by providing an abstract synchronization mechanism based on rendez-vous semantics. This enables the designer to specify high-level communication as well as low-level details such as signal transitions. Abstract synchronization events are expanded automatically to low-level handshake signals. We have developed a new algebra for communicating Petri nets that is applicable to general Petri nets, involves no unfolding, and defines hiding as generalized net contraction. We have developed methods based on this formal algebra that can be used to manipulate communicating interface modules, to verify their consistency, and to use them as a basis for optimizations.
Starting Page	49
Ending Page	55
File Size	97958
Page Count	7
File Format	PDF
ISBN	0897916530
ISSN	0738100X
DOI	10.1109/DAC.1994.204072
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1994-06-06
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Petri nets Optimization methods Hardware System-level design Signal design Very large scale integration Field programmable gate arrays Digital signal processing System buses Software systems
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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