NDLI: Parameterized Looped Schedules for Compact Representation of Execution Sequences in DSP Hardware and Software Implementation

Content Provider	IEEE Xplore Digital Library
Author	Ming-Yung Ko Zissulescu, C. Puthenpurayil, S. Bhattacharyya, S.S. Kienhuis, B. Deprettere, E.F.
Copyright Year	1991
Abstract	In this paper, we present a technique for compact representation of execution sequences in terms of efficient looping constructs. Here, by a looping construct, we mean a compact way of specifying a finite repetition of a set of execution primitives. Such compaction, which can be viewed as a form of hierarchical run-length encoding (RLE), has application in many very large scale integration (VLSI) signal processing contexts, including efficient control generation for Kahn processes on field-programmable gate arrays (FPGAs), and software synthesis for static dataflow models of computation. In this paper, we significantly generalize previous models for loop-based code compaction of digital signal processing (DSP) programs to yield a configurable code compression methodology that exhibits a broad range of achievable tradeoffs. Specifically, we formally develop and apply to DSP hardware and software synthesis a parameterizable loop scheduling approach with compact format, dynamic reconfigurability, and low-overhead decompression
Sponsorship	IEEE Signal Processing Society
Starting Page	3126
Ending Page	3138
Page Count	13
File Size	1078937
File Format	PDF
ISSN	1053587X
Volume Number	55
Issue Number	6
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-06-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Digital signal processing Hardware Compaction Very large scale integration Field programmable gate arrays Signal synthesis Encoding Application software Array signal processing Signal generators signal processing Design automation embedded systems field-programmable gate arrays (FPGAs) high-level synthesis program compilers reconfigurable design
Content Type	Text
Resource Type	Article
Subject	Signal Processing Electrical and Electronic Engineering

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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