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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Verlind, E. Kolks, T. de Jong, G. Bill Lin De Man, H. |
| Copyright Year | 1994 |
| Description | Author affiliation: IMEC, Leuven, Belgium (Verlind, E.) |
| Abstract | An important practical approach to automatic verification of finite state concurrent systems is temporal logic model checking. However, a major barrier towards wider application of suchmethods is the state explosion problem that often occurs during the composition of complex communicating systems. In addition to being large, many systems have very deep state spaces as well. In this paper, we propose an abstraction method based on time abstraction which can significantly reduce both the size as well as the depth of the state space that must be explored during model checking. It is especially suited for applications involving systems that are loosely coupled in the sense that communication activity is relatively sparse, such as applications involving DSPs, which have large intervals of autonomous processing, with communication activity in between. All properties expressiblewith the temporal logic CTL* or CTL* -X are strongly preserved under the proposed abstraction. In particular, we give a method that can replace a chain of states by a single state with atime label . The abstractedmodel is represented by means of atimed label transition system model. We give acomposition algorithm for composing the individually time abstracted models to form a global model that can be converted back to a conventional, but potentiallymuch reduced,state space suitable formodel checking. Furthermore, a similar approach can be followed in dealing with wait states in which a system is idling while waiting for an escape signal. For many cases, our approach is successful in alleviating the state explosion problemthat often arises in composition of communicating systems. |
| Starting Page | 609 |
| Ending Page | 614 |
| File Size | 124967 |
| Page Count | 6 |
| File Format | |
| ISBN | 0897916530 |
| ISSN | 0738100X |
| DOI | 10.1109/DAC.1994.204176 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1994-06-06 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Association for Computing Machinery, Inc. (ACM) |
| Subject Keyword | State-space methods Explosions Automatic logic units Digital signal processing Data structures Boolean functions Design methodology Formal verification Arithmetic |
| Content Type | Text |
| Resource Type | Article |
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