Please wait, while we are loading the content...
Please wait, while we are loading the content...
| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Nishimukai, T. |
| Copyright Year | 1994 |
| Description | Author affiliation: Central Research Laboratory, Hitachi, Ltd., Tokyo, Japan (Nishimukai, T.) |
| Abstract | Design methodologies for Hitachi's RISC microprocessors and microcontrollers are discussed. One of the processors is a high-end PA-RISCTM. The others, the PA/50 and the SH series microcontroller, are low power and low cost processors. Low cost processors require small chip sizeand short design time. To shorten the architecture level design time, we have developed a RT-level behavior simulation tool based on C language. And to reduce the total design time, we use a gate-level synthesis program from the behavior model description. This approach resulted in the low power 42 MIPS/W PA-RISCTM processor (the PA/50, which run at a 33 MHz clock rate) being completed within 15months. Another approach to minimizing chip size while maintaining high performance is to reduce the design turnaround time by using microcode instead of direct wired logic design. We wrote 480-word microcodes equivalent to a 5.8K transistor logic. After assigning the control stages for the microcode fields, we used an in-house logic synthesis and optimized for performance and chip size. The CPU core of the SH series microcontroller occupies only 8 mm2 including CPU core and multiplier circuit. The processor reaches 16 MIPS at 20 MHz. It took 17 man-months to realize a minimum 8 mm2 chip. The total control logic consists of 27 thousand transistors. |
| Starting Page | 592 |
| Ending Page | 593 |
| File Size | 93543 |
| Page Count | 2 |
| File Format | |
| ISBN | 0897916530 |
| ISSN | 0738100X |
| DOI | 10.1109/DAC.1994.204172 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1994-06-06 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Association for Computing Machinery, Inc. (ACM) |
| Subject Keyword | Microcontrollers Logic design Permission Clocks Computational modeling Logic gates Circuit synthesis Laboratories Trademarks Design automation |
| Content Type | Text |
| Resource Type | Article |
National Digital Library of India (NDLI) is a virtual repository of learning resources which is not just a repository with search/browse facilities but provides a host of services for the learner community. It is sponsored and mentored by Ministry of Education, Government of India, through its National Mission on Education through Information and Communication Technology (NMEICT). Filtered and federated searching is employed to facilitate focused searching so that learners can find the right resource with least effort and in minimum time. NDLI provides user group-specific services such as Examination Preparatory for School and College students and job aspirants. Services for Researchers and general learners are also provided. NDLI is designed to hold content of any language and provides interface support for 10 most widely used Indian languages. It is built to provide support for all academic levels including researchers and life-long learners, all disciplines, all popular forms of access devices and differently-abled learners. It is designed to enable people to learn and prepare from best practices from all over the world and to facilitate researchers to perform inter-linked exploration from multiple sources. It is developed, operated and maintained from Indian Institute of Technology Kharagpur.
Learn more about this project from here.
NDLI is a conglomeration of freely available or institutionally contributed or donated or publisher managed contents. Almost all these contents are hosted and accessed from respective sources. The responsibility for authenticity, relevance, completeness, accuracy, reliability and suitability of these contents rests with the respective organization and NDLI has no responsibility or liability for these. Every effort is made to keep the NDLI portal up and running smoothly unless there are some unavoidable technical issues.
Ministry of Education, through its National Mission on Education through Information and Communication Technology (NMEICT), has sponsored and funded the National Digital Library of India (NDLI) project.
| Sl. | Authority | Responsibilities | Communication Details |
|---|---|---|---|
| 1 | Ministry of Education (GoI), Department of Higher Education |
Sanctioning Authority | https://www.education.gov.in/ict-initiatives |
| 2 | Indian Institute of Technology Kharagpur | Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project | https://www.iitkgp.ac.in |
| 3 | National Digital Library of India Office, Indian Institute of Technology Kharagpur | The administrative and infrastructural headquarters of the project | Dr. B. Sutradhar bsutra@ndl.gov.in |
| 4 | Project PI / Joint PI | Principal Investigator and Joint Principal Investigators of the project |
Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon |
| 5 | Website/Portal (Helpdesk) | Queries regarding NDLI and its services | support@ndl.gov.in |
| 6 | Contents and Copyright Issues | Queries related to content curation and copyright issues | content@ndl.gov.in |
| 7 | National Digital Library of India Club (NDLI Club) | Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach | clubsupport@ndl.gov.in |
| 8 | Digital Preservation Centre (DPC) | Assistance with digitizing and archiving copyright-free printed books | dpc@ndl.gov.in |
| 9 | IDR Setup or Support | Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops | idr@ndl.gov.in |
|
Loading...
|