NDLI: Data Flow Partitioning for Clock Period and Latency Minimization

Content Provider	IEEE Xplore Digital Library
Author	Lung-Tien Liu Minshine Shih Chung-Kuan Cheng
Copyright Year	1994
Description	Author affiliation: Computer Science and Engineering, University of California, San Diego, La Jolla, CA (Lung-Tien Liu)
Abstract	We propose an efficientperformance-driven two-way partitioning algorithm to take into account clock cycle period and latency with retiming. We model the problem with a Quadratic Programming formulation to minimize the crossing edge count with nonlinear timing constraints. By using Lagrangian Approach on Modular Partitioning (LAMP), we merge nonlinear constraints to the objective function. The problem is then decomposed into primal and dual two subprograms. The primal and dual problems are solved by a Quadratic Boolean Programming approach and by a subgradient method using cycle mean method, respectively. Experimental results show our algorithm achieves an average of 23.25% clock cycle period and 19.54% latency reductions compared to the Fiduccia-Mattheyses algorithm. In terms of the average number of the crossing edges, our results are only 1.85% more.
Starting Page	658
Ending Page	663
File Size	247713
Page Count	6
File Format	PDF
ISBN	0897916530
ISSN	0738100X
DOI	10.1109/DAC.1994.204184
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1994-06-06
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Clocks Delay Quadratic programming Feedback loop Minimization methods Computer science Partitioning algorithms Timing Lagrangian functions Ear
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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