NDLI: All-out fight against yield losses by design-manufacturing collaboration in nano-lithography era

Content Provider	IEEE Xplore Digital Library
Author	Inoue, S. Kobayashi, S.
Copyright Year	2011
Description	Author affiliation: Advanced Lithography Process Technology Dept., Device Process Development Center, Toshiba Corporation, Corporate R&D Center (Inoue, S.; Kobayashi, S.)
Abstract	The concept of design-manufacturing collaboration for nano-lithography era has been clarified. The novel design-manufacturing system that the manufacturing tolerance reflecting design intention properly can be allocated to the layout has been proposed. According to the system, one can assign the “weak portion” explicitly on the layout, and can control the process for reducing the burden of manufacturing and further getting higher yield. More specifically, the extraction of electrically critical portion and conversion to the manufacturing tolerance has been demonstrated. The tolerance has applied to reduce computational burden of mask data preparation. Besides, the yield model-based layout scoring system has been also suggested to be significant remarkably. One can check the layout and modify not to loose the yield. Creation of yield function, layout scoring, and layout modification based upon the yield model have been demonstrated.
Starting Page	395
Ending Page	401
File Size	1453382
Page Count	7
File Format	PDF
ISBN	9781424475155
ISSN	21536961
e-ISBN	9781424475162
DOI	10.1109/ASPDAC.2011.5722220
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-01-25
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Layout Optimization Crosstalk Logic gates Lithography Collaboration
Content Type	Text
Resource Type	Article

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