NDLI: Emerging sensing techniques for emerging memories

Content Provider	IEEE Xplore Digital Library
Author	Yiran Chen Hai Li
Copyright Year	2011
Description	Author affiliation: Department of Electrical and Computer Engineering, University of Pittsburgh Pittsburgh, USA 15261 (Yiran Chen) \|\| Department of Electrical and Computer Engineering, Polytechnic Institute of New York University, Brooklyn, USA 11201 (Hai Li)
Abstract	Among all emerging memories, Spin-Transfer Torque Random Access Memory (STT-RAM) has shown many promising features such as fast access speed, nonvolatility, compatibility to CMOS process and excellent scalability. However, large process variations of both magnetic tunneling junction (MTJ) and MOS transistor severely limit the yield of STT-RAM chips. In this work, we present a recently proposed sensing technique called nondestructive self-reference read scheme (NSRS) to overcome the bit-to-bit variations in STT-RAM by leveraging the different dependencies of the high-resistance state of MTJs on the sensing current biases. Additionally, a few enhancement techniques including R-I curve skewing, yield-driven sensing current selection, and ratio matching are introduced to further improve the robustness of NSRS. The measurements of a 16Kb STT-RAM test chip shows that NSRS can significantly improve the chip yield by reducing sensing failures with high sense margin and low power consumptions.
Starting Page	204
Ending Page	210
File Size	466705
Page Count	7
File Format	PDF
ISBN	9781424475155
ISSN	21536961
e-ISBN	9781424475162
DOI	10.1109/ASPDAC.2011.5722185
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-01-25
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Magnetic tunneling Resistance Sensors Magnetization Switches Integrated circuits Magnetic fields
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Combined magnetic- and circuit-level enhancements for the nondestructive self-reference scheme of STT-RAM

A Precise Resistance Tracing Technique for a Toggle Mode MRAM Evaluation

A new self-reference sensing scheme for TLC MRAM

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