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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Kan Wang Yuchun Ma Sheqin Dong Yu Wang Xianlong Hong Cong, J. |
| Copyright Year | 2011 |
| Description | Author affiliation: Dept. of Electronic Engineering, Tsinghua University, Beijing, China, 100084 (Yu Wang) || Dept. of Computer Science, UCLA, Los Angeles, CA, 90095 (Cong, J.) || Dept. of Computer Science and Technology, Tsinghua University, TNList (Kan Wang; Yuchun Ma; Sheqin Dong; Xianlong Hong) |
| Abstract | Due to the increased power density and lower thermal conductivity, 3D is faced with heat dissipation and temperature problem seriously. Previous researches show that leakage power and delay are both relevant to temperature. The timing-power-temperature dependence will potentially negate the performance improvement of 3D designs. TSV (Through-Silicon-Vias) has been shown as an effective way to help heat removal, but they create routing congestions. Therefore, how to reach the trade-off between temperature, via number and delay is required to be solved. Different from previous works on TSV planning which ignored the effects of leakage power, in this paper, we integrate temperature-leakage-timing dependence into thermal via planning of 3D ICs. A weighted via insertion approach, considering both performance and heat dissipation with resource constraint, is proposed to achieve the best balance among delay, via number and temperature. Experiment results show that, with leakage power and resource constraint considered the temperature and via number required can be quite different, and weighted TSV insertion approach can improve thermal via number, by about 5.6%. |
| Starting Page | 261 |
| Ending Page | 266 |
| File Size | 972749 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781424475155 |
| ISSN | 21536961 |
| e-ISBN | 9781424475162 |
| DOI | 10.1109/ASPDAC.2011.5722195 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2011-01-25 |
| Publisher Place | Japan |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Delay Planning Through-silicon vias Temperature dependence Heating Tiles Three dimensional displays |
| Content Type | Text |
| Resource Type | Article |
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