NDLI: Case Studies on Transition Fault Test Generation for At-speed Scan Testing

Content Provider	IEEE Xplore Digital Library
Author	Zakaria, N.A. Bautista, E.V. Jusoh, S.B. Weng Fook Lee Xiaoqing Wen
Copyright Year	2010
Abstract	At-speed scan testing for intra-clock and inter-clock transition delay faults in a SOC design with multiple clock domains is an important and challenging issue. Current practice in industry usually applies a test scheme targeted on intra-clock transition fault delay testing (i.e., intra testing). In this paper a test scheme targeting both intra-clock and inter-clock domains for transition delay fault testing (i.e., intra-inter testing) is applied. This paper presents an empirical study by comparing between intra testing and intra-inter testing in terms of fault classification, test detection, test coverage, test volume, and test power by using industrial circuits. The information provided by this paper is beneficial to both practitioners and researchers in their pursuit of improving the quality of transition delay testing, which is critical to the quality of deep-sub micron VLSI chips.
Starting Page	180
Ending Page	188
File Size	416183
Page Count	9
File Format	PDF
ISBN	9781424484478
ISSN	15505774
DOI	10.1109/DFT.2010.29
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-10-06
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Clocks Circuit faults Delay Synchronization Logic gates Automatic test pattern generation launch-off-capture component transition delay fault intra-clock inter-clock test coverage
Content Type	Text
Resource Type	Article

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