NDLI: A Study of eSRAM Testability

Content Provider	IEEE Xplore Digital Library
Author	Takagi, N.
Copyright Year	2010
Abstract	In the market, consumers demand high performance, high quality, low power, low cost as well as increased functionality for VLSI. Scaling is the key factor for satisfying with these demands. Consumers also require realizing all of demands in as short development term as possible. VLSI venders, on the other hand, struggle with a lot of problems, such as prolonging development term, rising development cost, degrading quality, increasing test cost, and low yield. As scaling proceeding, we have to care about not only functional failures caused by macroscopic visible particles, but also parametric variations caused by atomic particles which has not been concerned with before. In addition, transistor variation caused by do pant fluctuations or surface roughness considerably affects a VLSI yield. Especially, eSRAM reveals unique failure modes that cannot be seen in logic circuits, because eSRAM is more susceptible to the variations than logic circuits. Increasing volume of eSRAM escalates the problem of low yield of VLSI. In contrast, taking an advantage of array structure in circuit and layout of eSRAM, we are able to identify locations and causes of the failures through a test sequence diagnosing the eSRAM failure modes. Information obtained from the test can be fed back to a fabrication process to decrease the failures. This feedback refines overall VLSI quality not only in eSRAM, but also in the other circuits, such as logic circuits and I/O. In this talk, I show firstly VLSI progress in the view of eSRAM. Next, I explain yield problems of today’s VLSI. Then, I describe the problems caused by increasing volume of eSRAM, the unique failure mode of eSRAM, and solutions for them. I discuss an important role of eSRAM to build up and maintain a VLSI fabrication line. Finally, I talk some hot topics about VLSI testing with eSRAM.
Starting Page	369
Ending Page	369
File Size	103988
Page Count	1
File Format	PDF
ISBN	9781424484478
ISSN	15505774
DOI	10.1109/DFT.2010.51
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-10-06
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Logic circuits Fabrication Arrays Surface roughness Fluctuations Testing Rough surfaces test eSRAM SRAM yield
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Synthesis of reversible circuits for testing with universal test set and C-testability of reversible iterative logic arrays

M-testability: an approach for data-path testability evaluation

Effects of surface roughness in inversion layer transport

Laser fabrication of micro-lens array on fused silica

Rapid Estimation of the Probability of SRAM Failure due to MOS Threshold Variations

Surface roughness influence on solderability

Reduction of test inputs for combinational circuits

A new low overhead design for testability of programmable logic arrays

Automated test bench for parameters measurement of surface roughness

A Study of eSRAM Testability

Similar Documents

Synthesis of reversible circuits for testing with universal test set and C-testability of reversible iterative logic arrays

M-testability: an approach for data-path testability evaluation

Effects of surface roughness in inversion layer transport

Laser fabrication of micro-lens array on fused silica

Rapid Estimation of the Probability of SRAM Failure due to MOS Threshold Variations

Surface roughness influence on solderability

Reduction of test inputs for combinational circuits

A new low overhead design for testability of programmable logic arrays

Automated test bench for parameters measurement of surface roughness

A Study of eSRAM Testability