NDLI: Dependability analysis using a fault injection tool based on synthesizability of HDL models

Content Provider	IEEE Xplore Digital Library
Author	Zarandi, H.R. Miremadi, S.G. Ejlali, A.
Copyright Year	2003
Description	Author affiliation: Dept. of Comput. Eng., Sharif Univ. of Technol., Tehran, Iran (Zarandi, H.R.; Miremadi, S.G.; Ejlali, A.)
Abstract	This paper presents a fault injection tool called SINJECT that supports several synthesizable and non-synthesizable fault models for dependability analysis of digital systems modeled by popular HDLs. The tool provides injection of transient and permanent faults into the Verilog as well as VHDL models of a digital circuit to study the fault behavior, fault propagation and fault coverage. Moreover, using specific simulators, the SINJECT provides a mixed-mode fault injection, i.e., fault injection into both Verilog and VHDL parts of a model, to achieve high description reality by Verilog and high capability modeling by VHDL. To demonstrate the tool, two case studies are evaluated: (1) an arithmetic processor with a non-synthesizable Verilog model, called ARP; and (2) a VHDL model of 32-bit processor with a synthesizable ALU, called DP32. The results show that depending on the fault injection points in the ARP, the effects of faults were significantly different, while in the case of DP32, the fault coverage varied between 51 to 56 percent of total faults injected.
Sponsorship	IEEE Comput. Soc. Test Technol. Tech. Council IEEE Comput. Soc. Tech. Committee on Fault-Tolerant Comput
Starting Page	485
Ending Page	492
File Size	306029
Page Count	8
File Format	PDF
ISBN	0769520421
ISSN	15505774
DOI	10.1109/DFTVS.2003.1250147
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-11-05
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Hardware design languages Fault tolerant systems Very large scale integration
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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