NDLI: A CAD tool for designing large, fault-tolerant VLSI arrays

Content Provider	IEEE Xplore Digital Library
Author	Poechmueller, P. Sharma, G.K. Glesner, M.
Copyright Year	1991
Description	Author affiliation: Darmstadt Univ. of Technol., Inst. of Microelectron. Syst., Germany (Poechmueller, P.)
Abstract	The authors describe implementation details of a CAD tool for efficient hardware realization of highly parallel algorithms. The Array Specification Language (ASL) of the tool allows the VLSI designer to specify the input not only at dependence graph level, but also at signal/data flow graph and/or array architecture level. Core of this tool is a multilevel functional-structural simulator, embedded into an environment supporting array processor design for real world applications. Another aspect of the tool is the intended support of advanced fault tolerance techniques in an early design phase. More emphasis is given to fabrication-time/run-time fault tolerance techniques and to find a cost-effective solution with the evaluation of optimality criteria and real design tradeoff.
Starting Page	132
Ending Page	137
File Size	423017
Page Count	6
File Format	PDF
ISBN	0818621702
DOI	10.1109/GLSV.1991.143955
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1991-03-01
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Design automation Fault tolerance Very large scale integration Hardware Parallel algorithms Specification languages Signal design Flow graphs Process design Runtime
Content Type	Text
Resource Type	Article

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