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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Young Su Kim Young Hun Kwon Ki Ho Kim Tae Woong Hwang Babulnath, R. Yu, C. Desai, P. |
| Copyright Year | 2012 |
| Description | Author affiliation: Wafer Inspection Division, KLA-Tencor Corporation, Milpitas, California (Babulnath, R.; Yu, C.; Desai, P.) || Yield Enhancement Team, System LSI Business, Samsung Electronics Co. Ltd, Yongin-City, Korea (Young Su Kim; Young Hun Kwon; Ki Ho Kim; Tae Woong Hwang) |
| Abstract | As design rules shrink, lithographers incorporate complex resolution enhancement techniques (RETs) that enable lithographers to extend existing lithographic processes to print features smaller than the wavelength of light used — a process called sub-wavelength lithography. These enhancements include optical proximity correction (OPC) and phase shift mask (PSM) technology, which together reduce the size and fine-tune the shape of features on the wafer. During the photolithography patterning process, marginal RET designs can print as out-of-focus features-or not print at all, creating open circuits that translate to electrical failures within the device. Two major variables, which affect the pattern printed on the wafer, are focus and exposure (dose). A number of techniques are used today to identify the process window accurately like Focus Exposure Matrix (FEM), CD $SEM^{1}$ and Process Window Qualification (PWQ). These techniques enable lithographers to understand the consequences of operating near the boundaries of the process window — allowing more informed decisions about whether to redesign the reticle or fine-tune inline defect and CD monitoring efforts to minimize the impact of the systematic defects on device yield. Particularly in back end of line (BEOL) After Develop Inspect (ADI) layers, nuisance defects (such as defects that are not visible on scanning electron microscope, defects on dummy structures, or other defects that do not affect yield) are so common, that sampling a statistically significant number of defects of interest (DOI) for PWQ becomes very time consuming and involves a lot of human effort. This paper describes the use of Design Based Classification (DBC) together with an AutoPWQ technique to improve time to results and to monitor BEOL ADI layers for process window drift. The combination of AutoPWQ + DBC method was compared to AutoPWQ alone as well as to FEM with manual sampling. |
| Starting Page | 327 |
| Ending Page | 331 |
| File Size | 806972 |
| Page Count | 5 |
| File Format | |
| ISBN | 9781467303507 |
| ISSN | 10788743 |
| e-ISBN | 9781467303514 |
| DOI | 10.1109/ASMC.2012.6212921 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2012-05-15 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Finite element methods Manuals Inspection Monitoring Qualifications Systematics Libraries DBC BEOL ADI PWQ |
| Content Type | Text |
| Resource Type | Article |
| Subject | Industrial and Manufacturing Engineering Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering |
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