NDLI: Newly developed ultralow CTE materials for thinner PKG applications

Content Provider	IEEE Xplore Digital Library
Author	Oohashi, K. Miyatake, M. Murai, H. Takanezawa, S. Tsuchikawa, S. Takekoshi, M. Kotake, T.
Copyright Year	2013
Description	Author affiliation: Tsukuba Res. Lab., Hitachi Chem. Co., Ltd., Chikusei, Japan (Miyatake, M.; Murai, H.; Takanezawa, S.; Tsuchikawa, S.; Takekoshi, M.; Kotake, T.) \|\| Printed Wiring Board Mater. R&D Dept., Hitachi Chem. Co., Ltd., Chikusei, Japan (Oohashi, K.)
Abstract	The higher density packaging technologies have been required to reduce the area of substrate for smaller portable handheld products and devices such as smart phones and tablet PCs. So, the three-dimensional packaging is becoming to be a key technology to minimize the total size of products and devices. However, the thinner construction of PoP (package on package) may cause the poor connection reliability because of the warpage of the substrate at the soldering process. So, the reduction of the warpage of the substrate by the ultralow CTE (coefficient of thermal expansion) materials may be the key to overcome. Recently, we have developed two types of ultralow CTE materials to meet with the requirement applying our new resin systems and a filler treatment technology. The developed materials show the ultralow CTE(X) of 2.8-3.3 $ppm/^{O}C$ which is close to that of the glass fabric. The resulted warpage using the material is much lower than that of the conventional low CTE material. We are also developing a technology for the further lowering of CTE for future applications.
Sponsorship	IEEE Orange County Sect. CPMT Chapt.
Starting Page	137
Ending Page	145
File Size	2099914
Page Count	9
File Format	PDF
ISBN	9781467360937
ISSN	15505723
e-ISBN	9781467360920
e-ISBN	9781467360913
DOI	10.1109/ISAPM.2013.6510397
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-02-27
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Abstracts Performance evaluation Silicon Assembly Absorption Resistance heating
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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