NDLI: Imperfection-immune Carbon Nanotube digital VLSI

Content Provider	IEEE Xplore Digital Library
Author	Patil, N. Mitra, S.
Copyright Year	2009
Description	Author affiliation: Department of Electrical Engineering and Department of Computer Science, Stanford University, Stanford, CA (Patil, N.; Mitra, S.)
Abstract	Carbon Nanotube Field Effect Transistors (CNFETs), consisting of semiconducting single-walled Carbon Nanotubes (CNTs), show great promise as extensions to silicon CMOS and in large-area electronics. While there has been significant progress at a single-device level, a major gap exists between such results and their transformation into VLSI CNFET technologies. Major CNFET technology challenges include mis-positioned CNTs, metallic CNTs, and wafer-scale processing. We present design and processing techniques to overcome these challenges. Experimental results demonstrate the effectiveness of the presented techniques. Mis-positioned CNTs can result in incorrect logic functionality of CNFET circuits. A new layout design technique produces CNFET circuits for arbitrary logic functions that are immune to a large number of mis-positioned CNTs. This technique is significantly more efficient compared to traditional defect- and fault-tolerance. Furthermore, it is VLSI-compatible and does not require changes to existing VLSI design and manufacturing flows. A CNT can be semiconducting or metallic depending upon the arrangement of carbon atoms. Typical CNT synthesis techniques yield ~33% metallic CNTs. Metallic CNTs create source-drain shorts in CNFETs resulting in excessive leakage (Ion/Ioff < 5) and highly degraded noise margins. We will present VLSI-compatible techniques for mitigating metallic CNT challenges. These techniques produce CNFET circuits with Ion/Ioff in the range of $10^{3}−10^{5},$ and overcome the limitations of existing metallic-CNT removal techniques. The above techniques are demonstrated for complex logic structures using wafer-scale growth of (99.5%) aligned CNTs on single-crystal quartz and wafer-scale CNT transfer from quartz to silicon. Such an integrated approach enables experimental demonstration of cascaded CNFET logic circuits.
Starting Page	1
Ending Page	1
File Size	257157
Page Count	1
File Format	PDF
ISBN	9781424450299
ISSN	10636404
DOI	10.1109/ICCD.2009.5413184
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-10-04
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Carbon nanotubes Very large scale integration Semiconductivity Silicon CMOS technology Logic circuits CNTFETs Process design Logic functions Fault tolerance
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
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7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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