NDLI: Fault-tolerant synthesis using non-uniform redundancy

Content Provider	IEEE Xplore Digital Library
Author	Woo, K.L. Guthaus, M.R.
Copyright Year	2009
Description	Author affiliation: Department of CE, University of California Santa Cruz, Santa Cruz, CA 95064 (Woo, K.L.; Guthaus, M.R.)
Abstract	As process technologies continue to scale into the nanometer regime, devices are becoming significantly more unreliable. Many forms of unreliability manifest as transient faults and can cause intermittent random logic upsets. These logic upsets are often caused by natural radiation (neutrons and alpha particles) or on-chip noise (cross-coupling, supply drop, or flicker noise). This research improves reliability by using non-uniform redundancy. Specifically, we present a dynamic programming algorithm that considers many possible topological redundancies, yet maintains a linear run-time due to efficient pruning of suboptimal solutions. Our algorithm provides designers with a Pareto-optimal set of solutions that trade reliability for area. Compared to existing Triple Modular Redundancy (TMR), we see similar reliability with only 35% area overhead instead of 326%.
Starting Page	213
Ending Page	218
File Size	640326
Page Count	6
File Format	PDF
ISBN	9781424450299
ISSN	10636404
DOI	10.1109/ICCD.2009.5413153
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-10-04
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Fault tolerance Redundancy Logic devices Logic programming 1f noise Nanoscale devices Neutrons Alpha particles Dynamic programming Heuristic algorithms
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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