NDLI: A robust pulsed flip-flop and its use in enhanced scan design

Content Provider	IEEE Xplore Digital Library
Author	Kumar, R. Bollapalli, K.C. Garg, R. Soni, T. Khatri, S.P.
Copyright Year	2009
Description	Author affiliation: Intel Corporation, Hillsboro, OR 97124 (Garg, R.) \|\| Department of ECE, Texas A&M University, College Station TX 77843 (Kumar, R.; Bollapalli, K.C.; Soni, T.; Khatri, S.P.)
Abstract	Delay faults are frequently encountered in nanometer technologies. Therefore, it is critical to detect these faults during factory test. Testing for a delay fault requires the application of a pair of test vectors in an at-speed manner. To maximize the delay fault detection capability, it is desired that the vectors in this pair are independent. Independent vector pairs cannot always be applied to a circuit implemented with standard scan design approaches. However, this can be achieved by using enhanced scan flip-flops, which store two bits of data. This paper has two contributions. First, we develop a pulsed flip-flop (PFF) design. Second, we present an enhanced scan flipflop design, based on our PFF circuit. We have compared the performance of our pulse based flip-flop with recently published pulse based flip-flop designs, as well as a traditional master-slave D flip-flop. Our PFF shows significant improvements in power and timing compared to the other designs. Our pulse based enhanced scan flip-flop (PESFF) has 13% lower power dissipation and 26% better timing than a conventional D flipflop based enhanced scan flip-flop (DESFF). The layout area of our PESFF is 5.2% smaller than the DESFF. Monte Carlo simulations demonstrate that our design is more robust to process variations than the DESFF.
Starting Page	97
Ending Page	102
File Size	361104
Page Count	6
File Format	PDF
ISBN	9781424450299
ISSN	10636404
DOI	10.1109/ICCD.2009.5413168
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-10-04
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Robustness Flip-flops Delay Circuit faults Circuit testing Timing Fault detection Production facilities Electrical fault detection Master-slave
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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