NDLI: Panoptic DVS: A fine-grained dynamic voltage scaling framework for energy scalable CMOS design

Content Provider	IEEE Xplore Digital Library
Author	Putic, M. Liang Di Calhoun, B.H. Lach, J.
Copyright Year	2009
Description	Author affiliation: Intel Corporation (Liang Di) \|\| University of Virginia (Putic, M.; Calhoun, B.H.; Lach, J.)
Abstract	The energy efficiency of a CMOS architecture processing dynamic workloads directly affects its ability to provide long battery lifetimes while maintaining required application performance. Existing scalable architecture design approaches are often limited in scope, focusing either only on circuit-level optimizations or architectural adaptations individually. In this paper, we propose a circuit/architecture co-design methodology called Panoptic Dynamic Voltage Scaling (PDVS) that makes more efficient use of common circuit structures and algorithm-level processing rate control. PDVS expands upon prior work by using multiple component-level PMOS header switches to enable fine-grained rate control, allowing efficient dithering among statically scheduled algorithms with sub-block energy savings. This way, PDVS is able to achieve a wide variety of processing rates to match incoming workload as closely as possible, while each iteration takes less energy to process than on architectures with coarser levels of rate control. Measurements taken from a fabricated 90nm test chip characterize both savings and overheads and are used to inform PDVS synthesis decisions. Results show that PDVS consumes up to 34% and 44% less energy than Multi-VDD and Single-VDD systems, respectively.
Starting Page	491
Ending Page	497
File Size	1118532
Page Count	7
File Format	PDF
ISBN	9781424450299
ISSN	10636404
DOI	10.1109/ICCD.2009.5413110
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-10-04
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Voltage control Dynamic voltage scaling Circuits Energy efficiency CMOS process Batteries Design optimization Process control Switches Scheduling algorithm
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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