NDLI: Timing variation-aware high-level synthesis considering accurate yield computation

Content Provider	IEEE Xplore Digital Library
Author	Jongyoon Jung Taewhan Kim
Copyright Year	2009
Description	Author affiliation: School of Electrical Engineering and Computer Science, Seoul National University, Korea (Jongyoon Jung; Taewhan Kim)
Abstract	This work proposes a new yield computation technique dedicated to HLS, which is an essential component in timing variation-aware HLS research field. The SSTAs used by the current timing variation-aware HLS techniques cannot support the following two critical factors at all: (i) non-Gaussian delay distribution of ‘module patterns’ used in scheduling and binding and (ii) correlation of timing variation between module patterns. However, without considering these factors, the synthesis results would be far less accurate in timing, being very likely to fail in timing closure. Even though there are advances in the logic level for SSTAs that support (i) and (ii), the manipulation and computation of (i) and (ii) in the course of scheduling and binding in HLS are unique in that there are no concepts of module sharing and performance yield computation in the logic level. Specifically, we propose a novel yield computation technique to handle the non-Gaussian timing variation of module patterns, where the sum and max operations are closed-form formulas and the timing correlation between modules used in computing performance yield is preserved to the first-order form. Experimental results show that our synthesis using the proposed yield computation technique reduces the latency by 24.1% and 28.8% under 95% and 90% performance yield constraints over that by the conventional HLS, respectively. Further, it is confirmed that our synthesis results are near optimal with less than 3.1% error on average.
Starting Page	207
Ending Page	212
File Size	396371
Page Count	6
File Format	PDF
ISBN	9781424450299
ISSN	10636404
DOI	10.1109/ICCD.2009.5413152
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-10-04
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Timing High level synthesis Delay Processor scheduling Distributed computing Logic Clocks Circuits Information technology Accuracy
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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