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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Gay, A. |
| Copyright Year | 1989 |
| Description | Author affiliation: IBM UK Lab. Ltd., Winchester, UK (Gay, A.) |
| Abstract | The heart of the IBM PS/2 Image Adapter is a VLSI display controller and processor chip utilizing an advanced 1- mu m standard-cell CMOS technology. This chip is 9.4 mm square and contains the standard-cell equivalent of 40000 two-input NAND gates, organized as a matrix of 27000 wireable cells. It is packaged in a 194-pin IBM pin grid array and consumes approximately 1 W. The display controller and processor chip contains most of the digital logic which gives the Image Adapter its high performance and function. It provides a programmable adapter which can be personalized for image, text, or graphics simply by providing a new microcode load for the on-chip processor. The Image Adapter performs algorithms such as image compression and graphics rotation at rates comparable to hardware, while retaining the flexibility of programmable microcode. A complete set of tools is provided for the processor, including a C language compiler, assembler, linker, simulator, and debugger.< |
| File Size | 598156 |
| File Format | |
| ISBN | 0818619406 |
| DOI | 10.1109/CMPEUR.1989.93357 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1989-05-08 |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Very large scale integration Displays Process control CMOS technology Logic arrays Graphics Heart CMOS process Packaging Adaptive arrays |
| Content Type | Text |
| Resource Type | Article |
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