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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Ramaswamy, S.V. Miller, G.D. |
| Copyright Year | 1993 |
| Description | Author affiliation: Dept. of Electr. Eng., Northern Illinois Univ., DeKalb, IL, USA (Ramaswamy, S.V.; Miller, G.D.) |
| Abstract | This paper describes the efficient implementation of the 2D DCT for image coding on the DSP96002 processor. The DSP96002 is a general purpose, dual-bus IEEE floating point digital signal processor. Utilizing the DSP96002's inherent parallel processing capabilities, the execution of a 8/spl times/8 fast 2D DCT takes 133 microseconds. The recently proposed 2D and 1D fast DCT algorithms are employed in this implementation. Transform coefficient zigzag ordering, used in the image coding process, executes in less than 28 microseconds. The fast DSP96002 routines, incorporated within this implementation, can be applied in a number of image coding applications such as video and still image coding as well as the newer JPEG still image and MPEG video standards.< |
| Starting Page | 96 |
| Ending Page | 99 |
| File Size | 345391 |
| Page Count | 4 |
| File Format | |
| ISBN | 0780317602 |
| DOI | 10.1109/MWSCAS.1993.343057 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1993-08-16 |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Discrete cosine transforms Image coding Signal processing algorithms Video compression Digital signal processing chips Transform coding Discrete transforms Digital signal processors Video signal processing Speech processing |
| Content Type | Text |
| Resource Type | Article |
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