NDLI: A new algorithm to construct parallel adder for high density codes

Content Provider	IEEE Xplore Digital Library
Author	Hashemian, R.
Copyright Year	1993
Description	Author affiliation: Dept. of Electr. Eng., Northern Illinois Univ., DeKalb, IL, USA (Hashemian, R.)
Abstract	A new method is presented for high-speed parallel addition. The method is shown to be highly efficient both in terms of silicon area consumption and speed. Here the addition is essentially performed by multiple but simultaneous incrementing procedure, called position-incrementing. The method also utilizes operand partitioning, much similar to the method implemented in carry select addition. The operands, after some initial treatments, are partitioned into small (4-bit) groups, and group additions are then performed independently and concurrently for both cases, one with input carry 1 and the other with 0. Next, the appropriate partial sums are selected based on the actual group carries which are separately processed in a multi-stage multiplexer structure. By implementing a recently developed incrementing circuit, and applying the carry select procedure it is shown that the operational delay is relatively small and it almost increases by O(log/sub 2/ n), where n is the word size. The algorithm is implemented for a 64-bit adder. The simulation results show high efficiency both in hardware as well as the speed (gate delays). For the 64-bit adder it is shown that the total hardware used is equivalent to 1186 gates (2 input NAND gates) and the maximum operational delay is about 7.5 unit gate delays.<>
Starting Page	851
Ending Page	854
File Size	434947
Page Count	4
File Format	PDF
ISBN	0780317602
DOI	10.1109/MWSCAS.1993.343202
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1993-08-16
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Multiplexing Hardware Parallel processing Added delay Algorithm design and analysis
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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