NDLI: A high speed and low power on CMOS/SOI technology and its modelings

Content Provider	IEEE Xplore Digital Library
Author	Lee, M. Asada, K.
Copyright Year	1993
Description	Author affiliation: Dept. of Electron. Eng., Tokyo Univ., Japan (Lee, M.; Asada, K.)
Abstract	Reduction of parasitic capacitances has predicted two-time high speed in deep-submicron CMOS/SIMOX ring oscillators (RO), where measurements are plotted for comparison with an analytical model with ultra-thin SOI film thickness of 30-nm and 50-nm. Analytical lower bounds for power dissipations of a CMOS/SOI inverter using a time-dependent capacitance model and the conventional model are propounded. It is concluded that (1) noticable results show high speed (24 ps/stage at the gate length of 0.15-/spl mu/m and supply voltage of 2.0 V) at 50-nm SOI-film thick and very low power (6 /spl mu/W/stage at the gate length, L/sub g/, of 0.2-/spl mu/m and supply voltage, V/sub dd/, of 1.5 V) at 30-nm SOI-film thick CMOS/SOI ring oscillator, while models at 30-nm SOI-film as poly-Si gate thickness decreases predicted comparable high speed (24 ps/stage at L/sub g/=0.1-/spl mu/m with V/sub dd/=2.5 V) like 50-nm SOI-film devices. This is promising for high performance of deep-submicron gate ultra-thin film CMOS/SOI technology at low voltage operations.<>
Starting Page	1040
Ending Page	1043
File Size	344693
Page Count	4
File Format	PDF
ISBN	0780317602
DOI	10.1109/MWSCAS.1993.343260
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1993-08-16
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	CMOS technology Semiconductor device modeling Parasitic capacitance Ring oscillators Voltage-controlled oscillators Capacitance measurement Thickness measurement Velocity measurement Analytical models Power dissipation
Content Type	Text
Resource Type	Article

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