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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Young, D. Lee Ming Cheng |
| Copyright Year | 1993 |
| Description | Author affiliation: Dept. of Electron. Eng., City Polytech. of Hong Kong, Kowloon, Hong Kong (Young, D.; Lee Ming Cheng) |
| Abstract | A general purpose low cost hardware ANN system has been built. The hardware is based on MD1220 neural bit slice and PC/AT is used as the host computer for testing. Each MD1220 contains 8 binary neurons. In order to improve its connectivity and flexibility, time division multiplexing (TDM) is used. This approach can allow network reconfiguration for different architectures by simply changing the firmware instead of modifying the hardware. Here, back propagation learning paradigm is selected for evaluating the system and a primitive OCR application was designed to test its functionality and feasibility. The results of this work are reported which indicate the implementation of neural network architectures using a conventional computer such as in the assembly code of 80286 may require 24 times more clock cycle than MD1220 assuming that the same clock (20 MHz) is used. Further analysis also indicates that the TDM approach will be a low cost and effective way of implementing the hardware ANN system. This is especially important for embedded controller application.< |
| Starting Page | 1185 |
| Ending Page | 1188 |
| File Size | 358783 |
| Page Count | 4 |
| File Format | |
| ISBN | 0780317602 |
| DOI | 10.1109/MWSCAS.1993.343305 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1993-08-16 |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Costs Time division multiplexing Artificial neural networks Computer architecture Clocks Testing Neurons Microprogramming Neural network hardware Optical character recognition software |
| Content Type | Text |
| Resource Type | Article |
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