NDLI: A design methodology for low power, reduced area, reliable CMOS buffers

Content Provider	IEEE Xplore Digital Library
Author	Cherkauer, B.S. Friedman, E.G.
Copyright Year	1994
Description	Author affiliation: Dept. of Electr. Eng., Rochester Univ., NY, USA (Cherkauer, B.S.; Friedman, E.G.)
Abstract	Circuit speed, power dissipation, physical area, and system reliability are the four performance criteria of primary concern in tapered buffer design. Each places a separate, often conflicting constraint on the design of a tapered buffer. This paper presents a unified design methodology for CMOS tapered buffers which permits trade-offs to be easily made among these four performance criteria. The methodology utilizes analytical expressions for each of the performance criteria. A process dependent look-up table is constructed based on these expressions and is used in conjunction with application-specific performance constraints to efficiently determine the optimal implementation for each particular buffer instantiation.
Starting Page	11
Ending Page	14
File Size	494592
Page Count	4
File Format	PDF
ISBN	0780324285
DOI	10.1109/MWSCAS.1994.519179
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1994-08-03
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Design methodology Power system modeling Power dissipation Semiconductor device modeling Circuits Capacitance Reliability Impedance Logic Propagation delay
Content Type	Text
Resource Type	Article

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A design methodology for low power, reduced area, reliable CMOS buffers