NDLI: Unification of speed, power, area, and reliability in CMOS tapered buffer design

Content Provider	IEEE Xplore Digital Library
Author	Cherkauer, B.S. Friedman, E.G.
Copyright Year	1994
Description	Author affiliation: Dept. of Electr. Eng., Rochester Univ., NY, USA (Cherkauer, B.S.; Friedman, E.G.)
Abstract	Circuit speed, power dissipation, physical area, and system reliability are the four performance criteria of concern in tapered buffer design. Each places a separate, often conflicting constraint on the design of a tapered buffer. Enhanced short-channel tapered buffer design equations are developed for propagation delay and power dissipation, as well as a new split-capacitor model of hot-carrier reliability and a two-component physical area model. Each performance criterion is independently investigated and analyzed, and the interaction of the four criteria is examined to develop both a qualitative and a quantitative understanding of the various design tradeoffs. These disparate approaches to tapered buffer design are unified into a convenient, integrated design methodology.<>
Starting Page	111
Ending Page	114
File Size	430005
Page Count	4
File Format	PDF
ISBN	078031915X
DOI	10.1109/ISCAS.1994.409210
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1994-05-30
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Propagation delay Power system reliability Circuits Power dissipation Equations Design methodology Semiconductor device modeling Capacitance Power system modeling Hot carriers
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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