NDLI: Design of tapered serial chains for reduced delay and power dissipation

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Design of tapered serial chains for reduced delay and power dissipation

Content Provider	IEEE Xplore Digital Library
Author	Cherkauer, B.S. Friedman, E.G.
Copyright Year	1994
Description	Author affiliation: Dept. of Electr. Eng., Rochester Univ., NY, USA (Cherkauer, B.S.; Friedman, E.G.)
Abstract	In this paper, the design issues relating to channel width tapered serially connected MOSFET chains are discussed. Channel width tapering is a method which is used to reduce the delay, area, and power dissipation of serial MOSFET chains. A design system for determining when tapering is appropriate, selecting the amount of tapering, and synthesizing the physical layout is presented. Physical layout issues unique to tapering are discussed, and fabricated test structures are described.
Starting Page	29
Ending Page	32
File Size	760960
Page Count	4
File Format	PDF
ISBN	0780324285
DOI	10.1109/MWSCAS.1994.519183
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1994-08-03
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Power dissipation MOSFET circuits Power MOSFET Propagation delay Circuit testing CMOS integrated circuits CMOS logic circuits Capacitance Integrated circuit synthesis Signal synthesis
Content Type	Text
Resource Type	Article

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