NDLI: A slice of a brain: a hybrid neural chip set

Content Provider	IEEE Xplore Digital Library
Author	Alhalabi, B.A. Bayoumi, M.A. El-Amawy, A.A.
Copyright Year	1994
Description	Author affiliation: Center for Adv. Comput. Studies, Southwestern Louisiana Univ., Lafayette, LA, USA (Alhalabi, B.A.; Bayoumi, M.A.; El-Amawy, A.A.)
Abstract	This paper proposes a complete self-contained chip set for ANN systems based on a back-propagation model with full-connectivity topology and on-chip learning and refreshing. We believe that our proposal is the first to offer fully hardware-supported on-board learning in continuous analog mode. Another unique novel feature of our 2-chip set design is that it does not require any other supporting chips of any kind and is capable of growing to any arbitrarily large size. Interface and communications with host and/or real-world systems is done via the direct analog and digital I/O ports which allow real-time computations. A representative system of 1 layer with 100 K analog synapses would require 100 SynChips and 20 NeuChips and expected to fill the entire surface of a whole wafer. Such a system which acquires an I/O port of up to 12800 digital bits or 3200 analog channels runs in absolute parallelism and would sustain a performance of 940x10/sup 12/ CPS. Larger systems may be constructed with several wafers.
Starting Page	489
Ending Page	494
File Size	745167
Page Count	6
File Format	PDF
ISBN	0780324285
DOI	10.1109/MWSCAS.1994.519285
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1994-08-03
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Neural network hardware Artificial neural networks Bandwidth Neurons Topology System-on-a-chip Proposals Real time systems Analog computers Computer interfaces
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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