NDLI: A framework for building cell libraries with novel devices

Content Provider	IEEE Xplore Digital Library
Author	Rehani, M. Rahman, S.U. Singh, G.
Copyright Year	1994
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Wayne State Univ., Detroit, MI, USA (Rehani, M.; Rahman, S.U.; Singh, G.)
Abstract	The decade of the nineties has witnessed a rapid growth in device technologies. Emerging devices can provide higher packaging density through vertical packing of lowered feature sizes, as well as allow fabrication using experimental materials with sub-threshold switching, opto-electronic, and superconducting properties. A lack of suitable simulation framework at the circuit level impedes the progress in rapidly developing circuit level models for putative applications. Circuit realization and simulation using commonly available suites of EDA tools is therefore desirable for the advancement of research in novel devices. A technique for overcoming this limitation using the currently available IC design tools is outlined in this paper. A "component library" consisting of primitive cells is developed and used for the automated development of higher level optimized cells. The higher level cells are generated using automated place and route tools and subsequently annotated with the pin delays obtained from the SPICE simulation. The optimized high level cells can be used in designing higher level systems and also be used in functional and timing verification on a digital simulation kernel. The only pre-requisite to the outlined approach is the existence of the SPICE models for devices that can allow modeling annotation of delays on the pins of the standard cells.
Starting Page	432
Ending Page	436
File Size	540488
Page Count	5
File Format	PDF
ISBN	0780324285
DOI	10.1109/MWSCAS.1994.519273
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1994-08-03
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Libraries Superconducting materials Circuit simulation Delay SPICE Packaging Fabrication Impedance Electronic design automation and methodology Design optimization
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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