NDLI: Low power LDPC decoder with efficient stopping scheme for undecodable blocks

Content Provider	IEEE Xplore Digital Library
Author	Mohsenin, T. Shirani-mehr, H. Baas, B.
Copyright Year	2011
Description	Author affiliation: University of Maryland, Baltimore County, United States (Mohsenin, T.) \|\| University of California, Davis, United States (Shirani-mehr, H.; Baas, B.)
Abstract	An efficient technique for early detection of undecodable blocks during LDPC decoding is introduced. The proposed method avoids unnecessary decoding iterations by predicting decoding failure and therefore results in significant improvement in power and latency in low SNR values. The proposed method which has a low hardware overhead compares the parity checksum against predefined threshold values for three iterations and terminates decoding if a condition is met. A 5.25 $mm^{2}$ 10GBASE-T Split-Row Threshold decoder is implemented using the proposed technique in 65 nm CMOS. The postlayout results show that at low SNR value of 3.0 dB, the decoder requires 2.3 times fewer decoding iterations which results in 23 pJ/bit energy dissipation. This is 2.4 times lower than the energy dissipation of Split-Row Threshold decoder without the proposed early stopping technique.
Starting Page	1780
Ending Page	1783
File Size	277937
Page Count	4
File Format	PDF
ISBN	9781424494736
ISSN	02714302
e-ISBN	9781424494743
e-ISBN	9781424494729
DOI	10.1109/ISCAS.2011.5937929
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-05-15
Publisher Place	Brazil
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Decoding Iterative decoding Bit error rate Signal to noise ratio Reactive power Partitioning algorithms 65 nm CMOS early termination undecodable blocks full parallel LDPC low power energy efficiency 10GBASE-T
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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