NDLI: Steady-State Analysis of Power Factor Correctors with a Fast Output-Voltage Feedback Loop

Content Provider	IEEE Xplore Digital Library
Author	Sebastian, J. Lamar, D.G. Hernando, M.M. Rodriguez, A. Fernandez, A.
Copyright Year	2009
Description	Author affiliation: Universidad de Oviedo. Grupo de Sistemas Electrónicos de Alimentación (SEA), Edificio Departamental no 3. Campus Universitario de Viesques. 33204 Gijón. SPAIN. sebas@uniovi.es (Sebastian, J.) \|\| Universidad de Oviedo. Grupo de Sistemas Electrónicos de Alimentación (SEA), Edificio Departamental no 3. Campus Universitario de Viesques. 33204 Gijón. SPAIN (Lamar, D.G.; Hernando, M.M.; Rodriguez, A.; Fernandez, A.)
Abstract	When a Power Factor Corrector (PFC) is designed with a fast output-voltage feedback loop, the study of the power stage varies in comparison with the one carried out with a slow output-voltage feedback loop. This is a consequence of the voltage ripple that appears in the control signal. The static behaviour of a PFC with a fast output-voltage feedback loop is studied in this paper using two parameters: the module of the relative voltage ripple on the control signal and its phase angle. The total power processed by the PFC depends on these parameters, which do not change with the load and which determine the Total Harmonic Distortion (THD) and the Power Factor (PF) at the input of the PFC. Furthermore, these parameters also determine the maximum power that can be processed by the converter while still complying with EN 61000-3-2 regulations for Class A and Class B equipment. When the converter must comply with the aforementioned regulations for Class C or Class D equipment, however, the compliance does not depend on the power processed by the PFC and not all the possible combinations of the relative ripple of the control signal and of its phase angle manage to comply with these regulations. As regards the bulk capacitor, its value for a given value of the output voltage ripple is also a function of both the aforementioned parameters. Finally, the study was verified by simulation and in a prototype.
Starting Page	970
Ending Page	976
File Size	3803098
Page Count	7
File Format	PDF
ISBN	9781424428113
ISSN	10482334
DOI	10.1109/APEC.2009.4802780
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-02-15
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Steady-state Reactive power Feedback loop Bandwidth Transient response Voltage control Galvanizing Total harmonic distortion Signal processing Energy management
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Steady-State Analysis and Modeling of Power Factor Correctors With Appreciable Voltage Ripple in the Output-Voltage Feedback Loop to Achieve Fast Transient Response

Study of the Power Factor Correctors with fast output-voltage feedback loop

Average Small-Signal Modelling of the Power Stage of Power Factor Correctors with a Fast Output-Voltage Feedback Loop

Analysis and Modeling of PFC with Appreciable Voltage Ripple to Achieve Fast Transient Response

AN ANALYSIS OF PFC CONVERTER WITH HIGH-SPEED DYNAMIC RESPONSE R Satish Kumar

On the Maximum Bandwidth Attainable by Power Factor Correctors with a Standard Compensator

A simple three-phase power factor corrector with improved harmonic distortion

Stability of the fast voltage control loop in power factor correctors

Single-phase active current-source rectifier operated with power factor and Distortion Power Factor control

Steady-State Analysis of Power Factor Correctors with a Fast Output-Voltage Feedback Loop

Similar Documents

Steady-State Analysis and Modeling of Power Factor Correctors With Appreciable Voltage Ripple in the Output-Voltage Feedback Loop to Achieve Fast Transient Response

Study of the Power Factor Correctors with fast output-voltage feedback loop

Average Small-Signal Modelling of the Power Stage of Power Factor Correctors with a Fast Output-Voltage Feedback Loop

Analysis and Modeling of PFC with Appreciable Voltage Ripple to Achieve Fast Transient Response

AN ANALYSIS OF PFC CONVERTER WITH HIGH-SPEED DYNAMIC RESPONSE R Satish Kumar

On the Maximum Bandwidth Attainable by Power Factor Correctors with a Standard Compensator

A simple three-phase power factor corrector with improved harmonic distortion

Stability of the fast voltage control loop in power factor correctors

Single-phase active current-source rectifier operated with power factor and Distortion Power Factor control

Steady-State Analysis of Power Factor Correctors with a Fast Output-Voltage Feedback Loop