NDLI: Impact of Bias and Device Structure on Gate Junction Temperature in AlGaN/GaN-on-Si HEMTs

Content Provider	IEEE Xplore Digital Library
Author	Schwitter, B.K. Parker, A.E. Mahon, S.J. Fattorini, A.P. Heimlich, M.C.
Copyright Year	1963
Abstract	The thermal impact of device bias-state and structures (such as source connected field plates, gate-pitch, back-vias, and number of gate fingers) in AlGaN/GaN-on-Si high electron mobility transistors (HEMTs) are measured using gate metal resistance thermometry (GMRT). The technique characterizes the thermal response of device gate metallization to determine the gate-epilayer junction temperature (T_j), which is directly influenced by the channel heat source due to its close proximity. It is found that low gate leakage levels in GaN HEMTs make them favorable candidates for GMRT. Bias-dependent self-heating, independent of power dissipation, is observed in the devices. Therefore, T_j of different device configurations are compared at constant bias state, as well as constant power density (3.75 W/mm) to improve accuracy. T_j reduction is observed at high drain bias due to the migration of the channel heat source toward the gate field plate edge. This provides independent experimental validation for a reported electrothermal model [7]. A 3-D thermal finite element method model is presented, which simulates measured T_j rise to within ~6% across a range of device configurations and operating conditions. This is ultimately made possible upon implementation of a thermal boundary resistance layer and extraction of its temperature response using GMRT data.
Sponsorship	IEEE Electron Devices Society
Starting Page	1327
Ending Page	1334
Page Count	8
File Size	2644183
File Format	PDF
ISSN	00189383
Volume Number	61
Issue Number	5
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-01-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Temperature measurement Logic gates Gallium nitride Heating HEMTs MODFETs Thermal conductivity thermal resistance. Electrothermal effects gallium nitride high electron mobility transistors (HEMTs) monolithic microwave integrated circuits (MMICs) semiconductor device testing temperature measurement thermal analysis thermal resistance
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

The Impact of Bias Conditions on Self-Heating in AlGaN/GaN HEMTs

An Electrothermal Model for Empirical Large- Signal Modeling of AlGaN/GaN HEMTs Including Self-Heating and Ambient Temperature Effects

Study of Gate Junction Temperature in GaAs pHEMTs Using Gate Metal Resistance Thermometry

Electrothermal Access Resistance Model for GaN-Based HEMTs

Electrothermal Mapping of AlGaN/GaN HEMTs Using Microresistance Thermometer Detectors

Simple and Accurate Method to Estimate Channel Temperature and Thermal Resistance in AlGaN/GaN HEMTs

Forward Bias Gate Breakdown Mechanism in Enhancement-Mode p-GaN Gate AlGaN/GaN High-Electron Mobility Transistors

Current Collapse Suppression by Gate Field-Plate in AlGaN/GaN HEMTs

Measurement of Channel Temperature in GaN High-Electron Mobility Transistors

Impact of Bias and Device Structure on Gate Junction Temperature in AlGaN/GaN-on-Si HEMTs

Similar Documents

The Impact of Bias Conditions on Self-Heating in AlGaN/GaN HEMTs

An Electrothermal Model for Empirical Large- Signal Modeling of AlGaN/GaN HEMTs Including Self-Heating and Ambient Temperature Effects

Study of Gate Junction Temperature in GaAs pHEMTs Using Gate Metal Resistance Thermometry

Electrothermal Access Resistance Model for GaN-Based HEMTs

Electrothermal Mapping of AlGaN/GaN HEMTs Using Microresistance Thermometer Detectors

Simple and Accurate Method to Estimate Channel Temperature and Thermal Resistance in AlGaN/GaN HEMTs

Forward Bias Gate Breakdown Mechanism in Enhancement-Mode p-GaN Gate AlGaN/GaN High-Electron Mobility Transistors

Current Collapse Suppression by Gate Field-Plate in AlGaN/GaN HEMTs

Measurement of Channel Temperature in GaN High-Electron Mobility Transistors

Impact of Bias and Device Structure on Gate Junction Temperature in AlGaN/GaN-on-Si HEMTs