NDLI: RF Performance of SOI CMOS Technology on Commercial 200-mm Enhanced Signal Integrity High Resistivity SOI Substrate

Content Provider	IEEE Xplore Digital Library
Author	Ben Ali, K. Neve, C.R. Gharsallah, A. Raskin, J.-P.
Copyright Year	1963
Abstract	RF performance of a 200-mm commercial-enhanced signal integrity high resistivity silicon-on-insulator (eSI HR-SOI) substrate is investigated and compared with its counterpart HR-SOI wafer. By measuring coplanar waveguide lines and substrate crosstalk structures, it is demonstrated that losses are completely suppressed leading to virtually lossless linear substrate. Moreover, a reduction of the second harmonic distortion by more than 25 dB is measured on eSI HR-SOI wafer compared with HR-SOI. Excellent matching between experimental dc and RF characteristics of fully depleted SOI MOSFETs measured on top of HR-SOI and eSI HR-SOI is demonstrated. Furthermore, digital substrate noise is reduced by more than 25 dB on eSI HR-SOI compared with HR-SOI, when injected noise varies from 500 kHz to 50 MHz. The eSI HR-SOI substrate is fully compatible with the CMOS process and could be considered as a promising solution for the RF front-end-modules integration and system-on-chip applications.
Sponsorship	IEEE Electron Devices Society
Starting Page	722
Ending Page	728
Page Count	7
File Size	1776983
File Format	PDF
ISSN	00189383
Volume Number	61
Issue Number	3
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-01-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Substrates Radio frequency Noise Silicon Crosstalk Conductivity Coplanar waveguides trap-rich layer Digital substrate noise enhanced signal integrity high resistivity silicon-on-insulator (eSI HR-SOI) fully depleted (FD) SOI MOSFET high resistivity (HR) SOI substrate nonlinearity
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Photo-Induced Coplanar Waveguide RF Switch and Optical Crosstalk on High-Resistivity Silicon Trap-Rich Passivated Substrate

A Simulation Study of Hot Carrier Effects in SoI-Like Bulk Silicon nMOS Device

RF Performance of a Commercial SOI Technology Transferred Onto a Passivated HR Silicon Substrate

Improvement of SOI MOSFET RF Performance by Implant Optimization

Low resistivity SOI for substrate crosstalk reduction

A microscopic interpretation of the RF noise performance of fabricated FDSOI MOSFETs

RF Harmonic Distortion of CPW Lines on HR-Si and Trap-Rich HR-Si Substrates

Compact Surface Potential Model for FD SOI MOSFET Considering Substrate Depletion Region

Effect of high-temperature electron irradiation in thin gate oxide FD-SOI n-MOSFETs

RF Performance of SOI CMOS Technology on Commercial 200-mm Enhanced Signal Integrity High Resistivity SOI Substrate

Similar Documents

Photo-Induced Coplanar Waveguide RF Switch and Optical Crosstalk on High-Resistivity Silicon Trap-Rich Passivated Substrate

A Simulation Study of Hot Carrier Effects in SoI-Like Bulk Silicon nMOS Device

RF Performance of a Commercial SOI Technology Transferred Onto a Passivated HR Silicon Substrate

Improvement of SOI MOSFET RF Performance by Implant Optimization

Low resistivity SOI for substrate crosstalk reduction

A microscopic interpretation of the RF noise performance of fabricated FDSOI MOSFETs

RF Harmonic Distortion of CPW Lines on HR-Si and Trap-Rich HR-Si Substrates

Compact Surface Potential Model for FD SOI MOSFET Considering Substrate Depletion Region

Effect of high-temperature electron irradiation in thin gate oxide FD-SOI n-MOSFETs

RF Performance of SOI CMOS Technology on Commercial 200-mm Enhanced Signal Integrity High Resistivity SOI Substrate