NDLI: Dual-Metal-Gate InAs Tunnel FET With Enhanced Turn-On Steepness and High On-Current

Content Provider	IEEE Xplore Digital Library
Author	Beneventi, G.B. Gnani, E. Gnudi, A. Reggiani, S. Baccarani, G.
Copyright Year	1963
Abstract	A novel approach to optimize tunnel field-effect transistors (TFETs) by technology computer-aided design simulations is reported. The most interesting outcome of our design effort is a dual-metal-gate (DMG) TFET, which features an inverse subthreshold slope (SS) significantly over more than five orders of magnitude of drain current, with a minimum value of 6 mV/decade sustained across one drain-current decade or more. The DMG-TFET simultaneously fulfills both the low-standby-power off-state current and the high-performance on-state current at a supply voltage of 0.5 V. Therefore, 25% reduction of static power consumption is expected compared with the 2020 International Technology Roadmap for Semiconductors requirements for multigate transistors.
Sponsorship	IEEE Electron Devices Society
Starting Page	776
Ending Page	784
Page Count	9
File Size	2626847
File Format	PDF
ISSN	00189383
Volume Number	61
Issue Number	3
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-01-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Doping Logic gates Transistors Junctions Tunneling IP networks Optimization tunnel field-effect transistors (TFET) Band-to-band tunneling (BTBT) dual-metal-gate (DMG) dual-metal-gate tunnel field-effect transistor (DMG-TFET) green transistors (gFET) InAs steep subthreshold slope
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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